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?1 CXB1561Q-Y 32 pin qfp (ceramic) e93615b6z s3r-ic for optical fiber cimmunication receiver description the CXB1561Q-Y achieves the 3r optical-fiber cimmunication receiver functions (reshaping, regenerating and retiming) on a single chip using with a saw filter. features 3r-ic with a built-in post-amplifier (saw filter system) signal interruption alarm output data shutdown function for signal interruption timing phase can be fine adjusted delay length for edge detector (differentiator) can be selected single 5v power supply absolute maximum ratings supply voltage v cc ?v ee ?.3 to +7.0 v operating case temperature t c ?5 to +125 ? storage temperaturetstg ?5 to +150 ? output current (surge current) io 0 to 50 (100) ma d/d input current iid ?00 to +400 a sc/sc input current iic ?00 to +400 a s1/s2 input voltage vis v cc to v ee + 1.2 v recommended operating conditions supply voltage v cc ?v ee 5.0 0.5 v operating case temperature t c ?0 to +85 ? structure bipolar silicon monolithic ic applications sonet: 622.08mbps, 155.52mbps fiber channel: 531.25mbps, 265.625mbp clock multiplication: x2, x4 sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits.
?2 CXB1561Q-Y block diagram vccd v ee d up down cap2 cap3 v ee sd v ee a d d cap1 cap1 s1 s2 v cc a sc sc v ee al sq sq v cc db v ee db sd v ee da ca ca v cc da q q v cc di v cc al limit amp d-ff delay delay2 delay1 peak hold peak hold alarm post amp differential v ee db v ee db 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1
?3 CXB1561Q-Y pin description pin no. symbol 1 vccd 0v positive power supply pin for digital block. equivalent circuit description typical pin voltage dc ac 2v ee d ?v negative power supply pin for digital block. 4 down ?.3v resistor connection pins for alarm level setting. up pin: when the resistance connection to this pin is increased, the alarm level becomes higher. down pin: when the resistance connected to this pin is increased, the alarm level becomes lower. 3 up ?.3v 1k 100 100 200 200 v ee a v cc a 0.8ma 0.8ma 3 4 6 cap3 ?.8v capacitance connection pins for alarm block peak hold circuit. (each pin incorporates a capacitance of approximately 10pf.) cap2 pin: peak hold capacitance connection pin for the post-amplifier signal output. cap3 pin: peak hold capacitance connection pin for the alarm level setting block. 5 cap2 ?.8v v cc a v ee a 80 5a 20a 5a 10p 10p 80 5 6 7v ee 5v negative power supply pin. 9sd alarm output pins. terminate these pins in 510 at v ee . 8sd ?.9v to ?.7v ?.9v to ?.7v v ee d v cc d 8 9 11 v cc db 0v positive power supply pin for differential circuit. 10 v ee db ?v negative power supply pin for differential circuit.
?4 CXB1561Q-Y pin no. symbol equivalent circuit description typical pin voltage dc ac ?.9v to ?.7v ?.9v to ?.7v ?.9v to ?.7v limiter amplifier input pins. ensure that these inputs are ac-coupled. 15 sc ?.3v 16 sc ?.3v negative power supply pin for limiter amplifier. 14 v ee al ?v differential output pins. 12 sq 13 sq v cc al v ee al 200 200 50 50 1k 1k 0.4ma 0.4ma 100p 15 16 v ee db v cc db v ee d 510 510 12 13 ?.9v to ?.7v 21 vccda 0v positive power supply pin for output circuit. positive power supply pin for internal digital circuit. positive power supply pin for limiter amplifier. 20 q ?.9v to ?.7v ?.9v to ?.7v 19 q 18 vccdi 0v 17 vccal 0v data signal output pins. terminate these pins in 50 at vtt = ?v. v ee da v cc da 19 20
?5 CXB1561Q-Y pin no. symbol equivalent circuit description typical pin voltage dc ac ?.9v to ?.7v ?.9v to ?.7v 25 v ee a ?v negative power supply pin for analog block. 24 v ee da ?v negative power supply pin for output circuit. 23 ca clock signal output pins. terminate these pins in 50 at vtt = ?v 22 ca v ee da v cc da 22 23 29 cap1 capacitance connection pins to determine the high cut-off frequency for post-amplifier feedback. 28 cap1 27 d ?.3v post-amplifier input pins. ensure that these inputs are ac-coupled. 26 d ?.3v ?.9v to ?.7v ?.9v to ?.7v v cc al v ee a 200 200 1k 1k 10k 10k 0.8ma 0.8ma 100p 200 200 28 29 27 26 32 vcca 0v positive power supply pin for analog block. 31 s2 ?.0v pulse width switchover input pin for differential circuit. s2: open low for 622mbps s2: high for 155mbps 30 s1 ?.0v delay switchover input pin for delay block. ? t = t (s1: high) t (s1: open low) = 134ps (typ. target) v cc d v ee d 20k 200 50k 0.1ma 31 v cc d v ee d 20k 200 50k 0.1ma 30
?6 CXB1561Q-Y electrical characteristics dc characteristics (vcc = 0v, v ee = ?v 10%, tc = ?0 to 85?) item supply current ca/ca, q/q high output voltage ca/ca, q/q low output voltage sd/sd high output voltage sd/sd low output voltage s1/s2 high input voltage s1/s2 low input voltage s1/s2 high input current s1/s2 low input current i ee v oh -vcc v ol -vcc v oh a-vcc v ol a-vcc v ih -vcc v il -vcc i ih i il termination: rt = 50 , v tt = ?v * 1 termination: rt = 50 , v tt = ?v termination: rt = 50 , v tt = ?v * 1 termination: rt = 50 , v tt = ?v termination: rt = 510 , to v ee * 1 termination: rt = 510 , to v ee termination: rt = 510 , to v ee * 1 termination: rt = 510 , to v ee ?57 ?.03 ?.15 ?.81 ?.86 ?.08 ?.20 ?.90 ?.95 ?.17 ?.00 ?0 ?10 ?4 ?.88 ?.88 ?.62 ?.60 ?.82 ?.83 ?.57 ?.55 0 ?.47 150 ma v ? symbol conditions min. typ. max. unit * 1 v ee = ?v, tc = 0 to 85? ac characteristics (vcc = 0v, v ee = ?v 10%, v tt = ?v, tc = ?0 to 85?) item data rate d/d input resistance d/d input identification max. voltage post amp gain sq output pulse width sq output amplitude sq rise time sq fall time sc/sc input resistance sc/sc input identification max voltage limit amp gain phase margin for the flip-flop block q/q rise time q/q fall time ca/ca rise time ca/ca fall time ca/ca output duty cycle da db r in m vmaxm gp t d1 t d2 vob trb tfb rinl vinl gl ? q trq tfq trc tfc du s2: open low s2: high for single-end input, dc cut-off i nternal signal: 400mv s2: open low s2: high output, dc cut-off, 50 load 50 load, 20% to 80% for single-end input, dc cut-off internal signal: 400mv 50 load, 20% to 80% 414.72 155.52 750 1000 45 525 1050 480 200 200 37.5 1000 30 320 200 200 150 120 45 622.08 311.04 1000 760 1625 670 300 300 50 340 440 410 245 215 50 1250 1075 2150 850 420 400 62.5 650 650 350 350 55 mbps mvp-p db ps mv ps mvp-p db deg ps % symbol conditions min. typ. max. unit
?7 CXB1561Q-Y item identification maximum voltage amplitude of alarm level hysteresis width sd/sd response assert time sd/sd response deassert time vmaxa ? p tas tdas d?ingle-phase input conversion * 2 low ? high * 2 high ? low * 2 6 12 100 100 mvp-p db ? symbol conditions min. typ. max. unit * 2 cap2/cap3 pin capacitance 470pf, v (up pin) ?v (down pin) = 10mv, d input voltage = 130mvp-p electrical characteristics measurement circuit for dc characteristics v v v v v v v tt 50 50 50 50 51 c6 c4 v sc 510 510 c8 c7 v down v up a a v a v ee v s 2 v s 1 c2 c3 c1 r d v d v v limit amp d-ff delay delay2 delay1 peak hold peak hold alarm post amp differential v ee db v ee db 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 30 2 2.5
?8 CXB1561Q-Y for ac characteristics 510 510 v down v up v ee v cc v s 2 v s 1 470pf v d 470pf 100pf 100pf 1000pf 1000pf oscilloscope high impedance input z0 = 50 z0 = 50 z0 = 50 z0 = 50 z0 = 50 z0 = 50 oscilloscope 50 w input 470pf 470pf v sc limit amp d-ff delay delay2 delay1 peak hold peak hold alarm post amp differential v ee db v ee db 0.033f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 a a
?9 CXB1561Q-Y application circuit v tt 51 51 51 51 51 c6 510 510 c8 c7 v ee c2 c1 r d v d limit amp d-ff delay delay2 delay1 peak hold peak hold alarm post amp differential v ee d b v ee d b c3 r d 1 9 8 2 7 r6 r5 c4 1000pf 51 51 1000pf saw 4 3 5 6 10 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 a application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?10 CXB1561Q-Y timing chart sectional waveforms of the application circuit alarm level set up by r5/r6 td tsa tdas 1 input (d) 2 post-amplifier output 3 differentiator output (sq) 4 saw output (sc) 5 limiter amplifier output 6 delay block output 7 shutdown signal 8 data output (q) 9 clock output (ca) 10 alarm output (sd) optical signal input status signal input signal interruption high level low level low level high level fixed at high level sd sd q alarm block logic only the data (q. q), not clock, is shut down for signal interruption.
?11 CXB1561Q-Y description of operation 1. overall operations the structure of optical-fiber communication receiver system is shown in fig. 1. the CXB1561Q-Y performs the 3r operations indicated below. photodiode .........converts a data optical signal to a current signal. pre amp..............converts a data current signal to a voltage signal (however, the voltage level is feeble). 3r .......................1) amplifies a feeble data voltage signal (reshaping). 2) outputs a data signal in sync with a clock signal (retiming). 3) outputs both data and clock signals as ecl level signals (regenerating). data signal clock signal 3r voltage signal current signal pre amp vcc optical signal fig. 1. optical fiber communication receiver system clock the signal flow of the CXB1561Q-Y, including the saw filter, is as shown in fig. 2. first, the feeble signal output of the pre-amplifier enters the post-amplifier and is amplified to an ic internal logic level. the amplified signal is then divided into the clock and data sides shown below. the clock side derives a clock signal from a data signal. first, the post-amplifier signal enters the differentiator, which generates a pulse output having an uniform width at the signal rise and fall times. this output pulse enters the saw filter, which generates resonance at regular intervals and outputs a sin wave having a resonance frequency. this signal output then enters the limiter amplifier and is amplified to an ic internal logic level. this amplified signal is used as the d- ff block clock signal. in the data side, on the other hand, the post-amplifier signal enters the delay section, where the signal is delayed to accomplish data/clock synchronization at the d-ff block. the signals separated into the clock and data sides are therefore synchronized with each other at the d-ff block and output to the outside. feeble signal (from pre-amplifier) post-amplifier differentiator delay saw limit amplifier d-ff data output clock signal clock side data side fig. 2. signal flow
?12 CXB1561Q-Y 2. delay length selection for edge detector (differentiator) (s2 pin operations) the larger the resonance frequency (saw filter) component in the input signal, the greater the saw filter output. therefore, the CXB1561Q-Y is designed to offer differing differentiator pulse widths in the 622.08mbps and 155.52mbps of the sonet. the pulse width varies as follows according to the s2 pin input. s2: open low ? for 622.08mbps, 531.25mbps s2: high ? for 155.52mbps, 265.625mbps 3. timing phase fine adjustment (s1 pin operations) as explained under overall operations, the data signal delay is adjusted by the delay block to synchronize the clock and data signals at the d-ff block. however, as the clock signal is output to the outside when it passes through the saw filter, the clock delay varies with the saw filter type and on-board wiring length. to compensate for such a clock external delay variations more or less, the delay provided by the data delay section can be varied by switching s1 pin input. the delay change ? t is set up as follows. ? t = t (s1: open low) ?t (s1: high) = 134ps (design target value) the above indicates that the delay provided by the data delay block is ? t greater when s1 is open low than when s1 is high. 4. alarm output and data shutdown functions when the input signal level is lower than the alarm setting level, the CXB1561Q-Y generates an alarm signal and forcibly places the data output on a high level. for alarm level identification, a comparator having a hysteresis function is used to prevent misoperations of alarm output. the hysteresis width is designed so that the gain is always maintained constant (design target value: 6db) without regard to the alarm setting level. the alarm level setting is determined by the voltage difference between pins 3 (up) and 4 (down). therefore, a desired voltage should be generated between the up and down pins and that the up pin voltage is higher than the down pin voltage.
?13 CXB1561Q-Y notes of operation 1. post-amplifier block in the post-amplifier block, the dc bias is automatically fed back by capacitors c1 and c2 as shown in fig. 3. so, input with the dc cut-off. external capacitor c1 and ic internal resistor r1 determine the low input cut-off frequency f2 for post-amplifier, and external capacitor c2 and ic internal resistor r2 determine the high cut-off frequency f1 for dc bias feedback. since peaking characteristics may occur in the lower frequency of the amplifier gain characteristics depending on the f1/f2 combination, set the c1 and c2 values so as to avoid the occurrence of peaking characteristics. the r1 and r2 target values and c1 and c2 typical values are as indicated below. when a single-ended input is used, provide ac grounding by connecting pin 27 to capacitor c3 that has the same capacitance as capacitor c1. as this circuit is designed for mark density 1/2.,it is not recommended to use for mark density substantially different from 1/2. r1 (internal) ? 1k f2 ? 340khz c1 (external) ? 470pf r2 (internal) ? 10k f1 ? 480hz c2 (external) ? 0.033uf 5 6 27 26 c1 c3 c2 r1 r1 r2 r2 to ic interior fig. 3. f1 f2 frequency gain feedback gain frequency response characteristic amplifier gain frequency response characteristic fig. 4.
?14 CXB1561Q-Y 2. limiter amplifier block in the limiter amplifier block, the dc bias is automatically fed back by capacitor c4 and ic internal capacitor c5 as shown in fig. 5. so, input with the dc cut-off. as is the case with the post-amplifier, external capacitor c4 and ic internal resistor r3 determine the low input cut-off frequency f2 of limiter amplifier. further, ic internal capacitor c5 and ic internal resistor r4 determine the high cut-off frequency f1 for dc bias feedback. since peaking characteristics may occur in the lower frequency of the amplifier gain characteristics depending on the f1/f2 combination, set the c4 value so as to avoid the occurrence of peaking characteristics. the r3, r4, and c5 target values and c4 typical value are as indicated below. when a single-ended input is used, provide ac grounding by connecting pin 16 to capacitor c6 that has the same capacitance as capacitor c4. r3 (internal) ? 50 f2 ? 32mhz c4 (external) ? 100pf r4 (internal) ? 1k f1 ? 1.6mhz c5 (internal) ? 100pf c4 c6 c5 r3 r3 r4 r4 to ic interior 16 15 fig. 5.
?15 CXB1561Q-Y 3. alarm block as shown in fig. 6, the alarm block requires alarm level setting external resistors r5 and r6 and peak hold capacitors c7 and c8. when the resistance value provided for resistor r5 is increased, the alarm setting level rises. when the resistance value provided for resistor r6 is increased, the alarm setting level lowers. however, the voltage of pin 3 should be higher than the voltage of pin 4. for the alarm level setting, see fig. 7. in the relationship between the alarm setting level and hysteresis width, the hysteresis width maintains a constant gain (design target value: 6db) as shown in fig. 8. external capacitors c7 and c8 are used for input signal and alarm level peak hold capacitance. the c7 and c8 capacitance values should be set so as to obtain desired assert time and deassert time settings for the alarm signal. the additional resistances r10 and r11 make deassert time smaller. the r5, r6, c7, and c8 typical values are as indicated below. (a capacitance of approximately 10pf is built in pins 5 and 6 respectively.) 6 5 4 3 from main amp peak hold peak hold sd sd vcca 10p c8 vcca 10p vcc c7 vcc r6 v ee r5 v ee r10 v ee r11 v ee fig. 6. r5 ? 5k + a r6 ? 5k c7, 8 ? 470pf ic interior ic exterior the values of r7, r8, and r9 are typical 4 3 ru v ee rd v ee 5k r9 100 r8 100 r7 1k vcca vas vdas 5.0 5.2 5.4 5.6 ru (k w ) 0 2 4 6 8 10 12 14 16 vas, vdas (mvp-p) fig. 7.
?16 CXB1561Q-Y 3db 3db alarm setting input level hysteresis input electric signal amplitude small great vas vdas low level high level sd output vdas ? deassert level vas ? assert level fig. 8. 4. saw peripheral board design in the signal flow from the differentiator through the saw filter to the limiter amplifier, the signal is output to the outside at the saw filter. to assure proper timing in the ic, therefore, the board wiring length must be appropriately designed. for the data and clock timing adjustment at the d-ff in the ic, the typ. state position must conform to fig. 9 because the d-ff phase margin is the greatest when the clock is positioned at the center of data. further, the min. state must comply with the d-ff setup time, and the max. state must conform to the d-ff hold time. since the clock signal occurs at regular intervals, synchronization must be accomplished at least at a certain integer multiple of the clock period. the above timing setup is derived from the equation below. the board wiring must therefore be designed to satisfy the equation.
?17 CXB1561Q-Y t = t (saw filter delay time) + t (wiring delay time) {+ t (delay time for the ic which amplifies the saw filter output when it is feeble)} (1) typical value construction shown in fig. 10-a): t(typ.) = (n + 3/4) * tsaw ?tsdc (typ.) construction shown in fig. 10-b): t(typ.) = (n + 1/4) * tsaw ?tsdc (typ.) (2) minimum value t (min.) > t (typ.) + tsff ?1/2 * tsaw + (tsdc (typ.) ?tsdc (min.)) (3) maximum value t (max.) < t (typ.) ?thff + 1/2 * tsaw + (tsdc (typ.) ?tsdc (max.)) fig. 9. d-ff timing from post-amplifier differentiator delay saw limiter amplifier d-ff clock side data side ic interior ic exterior 2 1 1 2 d-ff section clock signal d-ff section data signal data minimum pulse width t w tw/2 tsff thff min. typ. max. 12 13 15 16 saw v ee ic interior ic exterior 12 13 15 16 saw v ee ic interior ic exterior fig. 10-a) fig. 10-b)
?18 CXB1561Q-Y for the constants in the equation on the preceding page, see the table below. n = integer (0,1,2, ??? tsaw = saw resonance frequency cycle 622.08mbps ? tsdc = tsdc1 155.52mbps ? tsdc = tsdc2 s2 pin: open low ? t'sdc = tsdc s2 pin: high ? t'sdc = tsdc ? ? t item time difference for timing variable delay time d-ff setup time d-ff hold time tsdc1 tsdc2 ? t tsff thff 613 822 100 70 100 747 1050 134 929 1549 163 ps 622.08mbps 155.52mbps symbol min. typ. max. unit (vcc = 0v, v ee = ?v 10%, tc = 0 to 85?) when, for instance, the standard board wiring length is calculated for a data rate of 622mbps, the following result is obtained. tsaw = 1607.5ps assuming the absolute phase of saw filter = ?0deg; board wiring delay time ? 5.85ps/mm construction ? fig. 10-a) n = 0 under the above conditions, the following results. t (typ.) = (n+3/4) * tsaw ?tsdc (typ.) = (0 + 3/4) * 1607.5 ?747 = 458.6ps t wiring length (typ.) = t (typ.) ?tsaw filter = 458.6 ?1607.5 * (10/360) = 413.9ps wiring length (typ.) = t wiring length (typ)/(board wiring delay time) = 413.9/5.85 = 70.8mm 5. order of power on the CXB1561Q-Y has a number of power supplies. note that the ic may break down if the following power- on order is not observed (no problem occurs when all the power supplies are turned on simultaneously). (1) when all vcc power supplies are turned on first (the v cc a, v cc al, v cc d, v cc da, and v cc db may be turned in any order.) turn on the v ee power supplies in any order. (2) when all vee power supplies are turned on first (the v ee , v ee a, v ee al, v ee d, v ee da, and v ee db may be turned in any order.) turn on the v cc al, v cc da, and vccdb (in any order) ? the v cc d ? v cc a.
?19 CXB1561Q-Y 6. differential output waveform the dc cut-off capacitance is connected between the differential output block and saw filter as shown in fig. 11 so that the waveforms are varied according to the ratio of the high level and low level for the output waveform as shown in fig. 12. so, note that the waveforms are different for sq and sq. differential output block a1 a2 12 13 b1 b2 1000pf 50 w 50 w 1000pf saw v ee fig. 11. a1 a2 b1 b2 the high level for the sq output pulse close to 50% the high level for the sq output pulse close to 25% a2 a1 b2 b1 fig. 12.
?20 CXB1561Q-Y 7. evaluation board saw peripheral board design is important for system performance. fig.13 shows evaluation board for 622.08mbps and the characteristics of the test circuit (fig.14) is shown in fig.15 to 18. fig. 13. evaluation board pattern fig. 14. measurement circut v ee v tt v cc d d sd sd q front back q ca ca z = 50 w CXB1561Q-Y evaluation board d q ppg vcc = +2v, vee = ?v, vtt = gnd ppg: pulse pattern generator clock data q ca ca z = 50 w z = 50 w error det clock data oscilloscope 51 w vtt 51 w vtt
?21 CXB1561Q-Y fig. 15. error rate vs. input signal (mark density 1/2, pattern 2n23-1, tc = 27?) fig. 16. clock jitter vs. input signal (mark density 1/2, pattern 2n23-1, tc = 27?) aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa a a a a a a a a a a a a a a a a a a a a a a a a a a a 10-11 10-10 10-9 10-8 10-7 err ratio 10-6 10-5 10-4 3 3.5 v ee = ?.0v tc = 27? din = 622.08mbps pattern: prbs 2 23 ?1 din (mvp-p) 4 4.5 5 aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a 0 10 20 30 40 50 1 10 100 jitter (ps) 1000 din (mvp-p) tr tf
?22 CXB1561Q-Y fig. 17. jitter transfer (mark density 1/2, pattern 2n23-1, input voltage = 6mvp-p, tc = 27?) fig. 18. jitter tolerance (mark density 1/2, pattern 2n23-1, input voltage = 6mvp-p, tc = 27?)
?23 CXB1561Q-Y package outline unit: mm sony code eiaj code jedec code package structure lead treatment lead material package weight tin plating 42 alloy 32pin qfp (ceramic) 14.73 0.3 0.48 0.1 1.016 1 8 9 16 17 24 25 32 4.92 max 0.15 0.05 0.76 0?to 10 10.63 max (0.825) 0.635 0.125 qfp-32c-l01 xqfp023-g-0000-a ceramic 0.3g package material

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